@N|Running in 64-bit mode
@N: CD720 :"C:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\isplever_classic2_0\examples\tlc_engine_v1b\tlc_engine.vhd":10:7:10:16|Top entity is set to tlc_engine.
@N: CD630 :"C:\isplever_classic2_0\examples\tlc_engine_v1b\tlc_engine.vhd":10:7:10:16|Synthesizing work.tlc_engine.behavioral 
@N: CD233 :"C:\isplever_classic2_0\examples\tlc_engine_v1b\tlc_engine.vhd":43:22:43:23|Using sequential encoding for type state_typ
@N: CL201 :"C:\isplever_classic2_0\examples\tlc_engine_v1b\tlc_engine.vhd":58:8:58:9|Trying to extract state machine for register next_state

